Currently, in order to realize a narrow bezel, a Half-size Video Graphics Array (HVGA) product utilizes a dual-layer wirings design generally, as illustrated in FIG. 1. Gate signal lines such as G1, G3, G5, G7, G9, and so forth communicate via metal in a gate layer while gate signal lines such as G2, G4, G6, G8, and so forth communicate via metal in a source/drain layer. In the case of dual-layer wirings, a resistance difference between the two layers of metal is large, and a delay difference between gate signals from the gate layer and the source/drain layer in the two layers of metal is great due to factors such as a difference in film homogeneity and the like. Especially at a rear-end of a panel which is far away from an integrated circuit, such delay of the gate signals would affect a feed-through voltage ΔVp, which may affect a pixel voltage and in turn generate voltage difference, such that light and dark image sticking occurs for a gray scale picture. Regarding this problem, at present, the only way is to change the process on the panel side, however the verifying period for such change is long, and it is still possible that the change in the process might further worsen the above problem.